Method for fabricating semiconductor package and semiconductor package using the same

• Main Authors: KIM, YOUNG-RAE, YUN, SEOK-WOO, AHN, SEO-YEON, SONG, YONG, PAEK, JONG-SIK, KIM, HUI-TAE, PARK, DOO HYUN, SUNG, PIL-JE
• Format: Patent
• Language: Chinese; English
• Published: 01.05.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die.