Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW)

A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at...

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Bibliographic Details
Main Authors BOSTLEY, PHIL J, TOUZNI, AZZEDINE, ZENG, THOMAS, TZENG, TZUNG REN
Format Patent
LanguageChinese
English
Published 16.12.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (SI) page table is stored, the MMU uses the IP A to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.
Bibliography:Application Number: TW20143107028