A state retention circuit adapted to allow its state integrity to be verified

• Main Author: FLYNN, DAVID WALTER
• Format: Patent
• Language: Chinese; English
• Published: 16.07.2013
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output. When the scan enable signal is not asserted, the state retention circuit outputs at the scan output a parity value, wherein the parity value is generated by combinatorial function circuitry on the basis of the state value and the scan input value, wherein the combinatorial function circuitry is configured such that the parity value inverts if either the state value or