Standard cell architecture using double poly patterning for multi VT devices

• Main Authors: KAMAL, PRATYUSH, CHIDAMBARAM, PR, PATEL, PRAYAG B, GAN, CHOCK H, SWAMYNATHAN, CHETHAN, VANG, FOUA
• Format: Patent
• Language: Chinese; English
• Published: 16.12.2012
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.