Semiconductor device

The write disturbance margin of reference cells that generate reference current during reading is improved. The bit line (BL) forms a clad wiring structure (40) in the normal cell region (10N) where normal memory cells (NMC0-NMC2) are disposed and a partially- or non-clad wiring structure (42) in th...

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Bibliographic Details
Main Authors TSUJI, TAKAHARU, WATANABE, GENTA
Format Patent
LanguageChinese
English
Published 01.03.2011
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The write disturbance margin of reference cells that generate reference current during reading is improved. The bit line (BL) forms a clad wiring structure (40) in the normal cell region (10N) where normal memory cells (NMC0-NMC2) are disposed and a partially- or non-clad wiring structure (42) in the reference cell region (10R) where the reference cell (RMC) is disposed. Thus, the write magnetic field intensity applied to the reference cell is smaller than the write magnetic field intensity applied to a normal memory cell during identical write currents.
Bibliography:Application Number: TW201099107505