Low cost fabrication of double box back gate silicon-on-insulator wafers

A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper ins...

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Bibliographic Details
Main Authors OTT, JOHN A, SHI, LEATHEN, DENNARD, ROBERT H, SADANA, DEVENDRA K, CHU, JACK O
Format Patent
LanguageChinese
English
Published 16.11.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer.
Bibliography:Application Number: TW20100100158