Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel and substrate panel
A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
01.05.2009
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. |
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Bibliography: | Application Number: TW200897121311 |