Processor system and exception handling method

This invention provides a microprocessor of collateral coprocessor capable of not processing the instruction address memory when there is an error and executing the instruction reverting control after the error treatment is finished. In the processor system, under the condition that an error is dete...

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Bibliographic Details
Main Authors NAKATA, HIROAKI, IZUHARA, FUMITAKA, YUASA, TAKAFUMI, AKIE, KAZUSHI, HOSOGI, KOJI, EHAMA, MASAKAZU
Format Patent
LanguageChinese
English
Published 01.02.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:This invention provides a microprocessor of collateral coprocessor capable of not processing the instruction address memory when there is an error and executing the instruction reverting control after the error treatment is finished. In the processor system, under the condition that an error is detected out by an error detection part, the error detection part (120) outputs an error signal to an interruption control part (64), the interruption control part (64) outputs the value of an error address register (61) and a control signal to a program counter control part (20), and the value of the program counter (21) is changed to the value of the error address register (61) so as to achieve the transferring treatment based on the error interruption treatment.; So, when the error is detected out, then the treatment of the value of the program counter (21) is not processed, the special memory register is not set and a control circuit which is recovered to the address when the error is happened after the error treat
Bibliography:Application Number: TW200897112663