Stress layer structure

A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each...

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Bibliographic Details
Main Authors LIU, CHIHIEN, YANG, CHIN-SHENG
Format Patent
LanguageChinese
English
Published 01.11.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the stress patterns is disposed on the substrate of each of the active regions, respectively. The partition line exposes a portion of the substrate and divides the two adjacent stress patterns. The dummy stress pattern is disposed on the substrate in the partition line.
Bibliography:Application Number: TW20070114212