Methods and systems for centralized dynamic link configuration (CDLC)
An embodiment of a method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset, comprises the following steps. The processor notifies to the chipset with CDLC enabling. The chipset issues a command to the processor after receiving the notification of CDLC enablin...
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Main Author | |
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Format | Patent |
Language | Chinese English |
Published |
01.11.2008
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Subjects | |
Online Access | Get full text |
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Summary: | An embodiment of a method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset, comprises the following steps. The processor notifies to the chipset with CDLC enabling. The chipset issues a command to the processor after receiving the notification of CDLC enabling. The processor broadcasts a preparation completion signal to the chipset after receiving the command. The chipset asserts a signal and activates a timer after receiving the preparation completion signal. The processor configures electronic devices thereof corresponding to a bus according to one of plurality sets of first link management mode (LMM) configuration parameters of a first LMM register indicated by a first link management action field (LMAF) code of a first LMAF register when detecting that the signal is asserted. The chipset configures electronic devices thereof corresponding to the bus according to one of plurality sets of second LMM configuration parameters of a second LMM register indicated by a sec |
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Bibliography: | Application Number: TW20070113487 |