Etching process to avoid polysilicon notching

• Main Authors: CHEN, CHIA-JEN, CHIU, YUAN-HUNG, TAO, HUN JAN, WANG, SHIANG-BAU, CHANG, MINGING, LIN, LI-TE
• Format: Patent
• Language: Chinese; English
• Published: 16.07.2006

A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a polysilicon layer on the gate dielectric; pattering a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portion of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.