ASIC clock floor planning method and structure

A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the...

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Bibliographic Details
Main Authors ARTHANARI, GEETHA, MENARD, DANIEL R, LASHER, MARK R, CARRIG, KEITH M
Format Patent
LanguageChinese
English
Published 01.06.2005
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree.
Bibliography:Application Number: TW200392133498