Coverage decoder circuit for performance counter

Circuitry (50) for use with a general purpose performance counter ("GPPC")(200) connected to a bus (104) carrying a plurality of encoded state coverage signals(502) indicative of test coverage in a logic design, wherein the circuitry(500) is operable to decode and capture the encoded cover...

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Bibliographic Details
Main Author ADKISSON, RICHARD W
Format Patent
LanguageChinese
English
Published 16.12.2004
Subjects
CALCULATING
COMPUTING
CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
GENERATION
PHYSICS
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Summary:Circuitry (50) for use with a general purpose performance counter ("GPPC")(200) connected to a bus (104) carrying a plurality of encoded state coverage signals(502) indicative of test coverage in a logic design, wherein the circuitry(500) is operable to decode and capture the encoded coverage information. A selection circuit (204/206) associated with the GPPC (200) is operable to select the encoded state coverage signals (502) from a multi-bit event signal (400) on the bus (104). A line decoder (504) coupled to the selection circuit (204/206) decodes the encoded state coverage signals (502) into N one-hot signals (506), which are asserted based on coverage of corresponding states during test. A capture circuit (508) is operable to capture the N one-hot signals (506) for further processing.
Bibliography:Application Number: TW20030132595