Address decode

Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory with the processor decoded address...

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Bibliographic Details
Main Authors DODD, JAMES M, MILSTREY, ROBERT
Format Patent
LanguageChinese
English
Published 01.10.2004
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory with the processor decoded address without decoding the address itself. In other embodiments, a processor or other external components provide a memory controller with partially decoded memory addresses. The memory controller then generates a decoded address from the partially decoded address and may access the memory with the generated decoded address.
Bibliography:Application Number: TW20030122743