Interconnect structure and method for forming

An interconnect structure with a via (66) embedded in a first low dielectric constant material (44) and a trench (66) embedded in a second low dielectric constant material (48), which is a different material than the first low dielectric constant material (44), is formed. In one embodiment, the seco...

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Bibliographic Details
Main Authors GOLDBERG, CINDY K, LII, YEONG-JYN T
Format Patent
LanguageChinese
English
Published 16.02.2004
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An interconnect structure with a via (66) embedded in a first low dielectric constant material (44) and a trench (66) embedded in a second low dielectric constant material (48), which is a different material than the first low dielectric constant material (44), is formed. In one embodiment, the second low dielectric constant material (48) is used as a mask for etching the first low dielectric constant material (44). Also, in one embodiment, the first low dielectric constant material (44) may be used as an etch stop layer for etching the second low dielectric constant material. The second low dielectric constant material (48) may include silicon and oxygen and the first low dielectric constant material (44) may be organic.
Bibliography:Application Number: TW20030117430