A METHOD TO FORM VERY HIGH MOBILITY VERTICAL CHANNEL TRANSISTOR BY SELECTIVE DEPOSITION OF SIGE OR MULTI-QUANTUM WELLS (MQWS)

• Main Authors: JIA ZHEN ZHENG, RAVI SUNDARESAN, YELEHANKA RAMACHANDRAMURTHY PRADEEP, YANG PAN, ELGIN QUEK, JAMES YONG MENG LEE, YING KEUNG LEUNG, LAP CHAN
• Format: Patent
• Language: English
• Published: 27.11.2003
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate (10) having an upper surface is provided. A high doped N-type lower epitaxial silicon layer (12) is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer (14) is formed on the lower epitaxial silicon layer (12). A high doped N-type upper epitaxial silicon layer (16) is formed on the middle epitaxial silicon layer (14). The lower, middle, and upper epitaxial silicon layers (12,14,16) are etched to form a epitaxial layer stack defined by isolation trenches (20,22). Oxide (24) is formed within the isolation trenches (20,22), The oxide (24) is etched to form a gate trench (26) within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice (28) is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer (30) is formed on the multi-quantum wells or the stained-layer super lattice (28) and within the gate trench. A gate conductor layer (32) is formed on the gate dielectric layer (30), filling the gate trench.