METHOD FOR FORMING A TRANSISTOR GATE DIELECTRIC WITH HIGH-K AND LOW-K REGIONS

• Main Authors: YELEHANKA RAMACHANDRAMURTHY PRADEEP, JIA ZHEN ZHENG, RAVI SUNDARESAN, YANG PAN, JAMES YONG MENG LEE, ELGIN QUEK, YING KEUNG LEUNG, LAP CHAN
• Format: Patent
• Language: English
• Published: 27.10.2003
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.