A WAFER LEVEL PACKAGE AND A METHOD OF FORMING THE SAME

According to embodiments of the present invention, a wafer level package is provided. The wafer level package includes at least one chip comprising at least one electronic component, and at least one connecting chip comprising at least one through-silicon via, wherein the at least one through-silico...

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Bibliographic Details
Main Authors KHOO YEE MONG, CHE FAXING, LI RUI, HO SOON WEE DAVID, NAVAS KHAN ORATTI KALANDAR, CHONG SER CHOONG, GAO SHAN, LIM TECK GUAN, LIM YING YING
Format Patent
LanguageEnglish
Published 27.09.2012
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:According to embodiments of the present invention, a wafer level package is provided. The wafer level package includes at least one chip comprising at least one electronic component, and at least one connecting chip comprising at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.Figure 3
Bibliography:Application Number: SG20120013678