INTEGRATED CIRCUIT HAVING ULTRALOW-K DIELECTRIC LAYER

INTEGRATED CIRCUIT HAVING ULTRALOW-K DIELECTRIC LAYER A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the devic...

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Bibliographic Details
Main Authors HUANG LIU, WIDODO JOHNNY, LENG LIM SIN
Format Patent
LanguageEnglish
Published 29.07.2008
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Summary:INTEGRATED CIRCUIT HAVING ULTRALOW-K DIELECTRIC LAYER A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.
Bibliography:Application Number: SG20070185937