Data processor having dynamic bus sizing

In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer o...

Full description

Saved in:
Bibliographic Details
Main Authors CRUDELE LESTER M, TIETJEN JAMES L, THOMPSON ROBERT R, MOTHERSOLE DAVID S
Format Patent
LanguageEnglish
Published 21.01.1994
Edition3
Subjects
CALCULATING
CHEMISTRY
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
HETEROCYCLIC COMPOUNDS
METALLURGY
ORGANIC CHEMISTRY
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.
Bibliography:Application Number: SG19930001198