VISIBLE ALIGNMENT MARKERS/LANDMARKS FOR CAD-TO-SILICON BACKSIDE IMAGE ALIGNMENT

• Main Authors: ALSTON, Michael Duane, RANGANATHAN, Lavakumar, MALABRY, Mickael Sebastien Alain, BUNNALIM, Hadi, SALEM, Rami Fathy Amin Gomaa, ENDRINAL, Lesly Zaren Venturina
• Format: Patent
• Language: English
• Published: 28.05.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.