QUICK ENERGY EFFICIENT REBOOT FROM ULTRA-LOW POWER MODE FOR A SYSTEM ON A CHIP

• Main Authors: PULIVENDULA, Deva Sudhir Kumar, DEVARASETTY, Venkata, GUDIPUDI, Srikanth, GUPTA, Nikesh
• Format: Patent
• Language: English
• Published: 27.09.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 20 September 2018 (20.09.2018) WIP0 I PCT ill IIIIIl °million °nolo om IIIII o!IIIIIIIIII o iflom oimIE (10) International Publication Number WO 2018/169669 Al (51) International Patent Classification: GOOF 1/32 (2006.01) GOOF 21/57 (2013.01) GOOF 9 / 4 401 (2018.01) (21) International Application Number: PCT/US2018/019710 (22) International Filing Date: 26 February 2018 (26.02.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/458,843 14 March 2017 (14.03.2017) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration, 5775 Morehouse Dri- ve, San Diego, California 92121-1714 (US). (72) Inventors: PULIVENDULA, Deva Sudhir Kumar; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). DEVARASETTY, Venkata; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). GUPTA, Nikesh; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). GUDIPUDI, Srikanth; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (74) Agent: WORLEY, Eugene; Loza & Loza, LLP, 305 North Second Avenue #127, Upland, California 91786 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). = (54) Title: QUICK ENERGY EFFICIENT REBOOT FROM ULTRA-LOW POWER MODE FOR A SYSTEM ON A CHIP (57) : A method for reducing power in a system is provided accord- 900 ing to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the 910 sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collaps- ing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip. 4 Collapse multiple power supply rails on the chip / 920 Exit the sleep state 922 Restore power to the multiple power supply rails Take the volatile memory out of the self-refresh mode Run the one or more binary images on one or more sub-systems on the chip 924 7 z 926 FIG. 9 [Continued on next page] Enter a sleep state Place the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state -912 W O 20 18/ 169669 Al WO 2018/169669 Al MIDEDIMOMMIDEFIEDEMIEHEIMOHOMEMOIMIE Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(11)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: - with international search report (Art. 21(3))