LOW-LATENCY OPTICAL CONNECTION FOR CXL FOR A SERVER CPU

A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream dire...

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Bibliographic Details
Main Authors MAHESH KUMASHIKAR, MD ALTAF HOSSAIN, ANKIREDDY NALAMALPU, ANSHUMAN THAKUR, DHEERAJ SUBBAREDDY
Format Patent
LanguageEnglish
Published 03.06.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.
Bibliography:Application Number: NL20212029099