HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD

• Main Authors: NIKHIL GUPTA, YOGESH BANSAL, MICHAEL HAAK, VIVEK GARG, NAZAR HAIDER, TIMOTHY YEE-KWONG KAM, ANDREW HERDRICH, RUPAL PARIKH, DORIT SHAPIRA, UJJWAL GUPTA, KRISHNAKANTH SISTLA, DEAN MULLA, PAVITHRA SAMPATH, NIKETHAN SHIVANAND BALIGAR, NILANJAN PALIT, STEPHEN PAUL HAAKE, RIPAN DAS, STEPHEN WANG, SHRUTHI VENUGOPAL, AMAN SEWANI, SURESH UDUPATI, ANKUSH VARMA, ADWAIT PURANDARE, STANLEY CHEN, ERIC DEHAEMER, PHANI KUMAR KANDULA
• Format: Patent
• Language: English
• Published: 24.05.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SOC). HPM provides a basis for managing power and thermals across a diverse set of dice.