FET VOLTAGE LEVEL DETECTING CIRCUIT

• Main Authors: FUAD HANNA MUSA, PERN SHAW
• Format: Patent
• Language: English
• Published: 31.12.1986
• Edition: 4
• Subjects: CONTROLLING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; REGULATING; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES; TESTING

There is provided a voltage level detecting circuit useful as power-up/power-down voltage indicator for a field effect transistor integrated circuit. A constant voltage reference generator is provided by a depletion type transistor in series with two enhancement type transistors coupled between power supply terminals of the integrated circuit chip. Each of the enhancement type transistors have their gate electrodes connected to their drain electrodes while the depletion type transistor has its gate electrode connected to the more negative or reference terminal of the power supply voltage. A constant voltage output is taken from between the junction of one of the enhancement mode transistors and the depletion type transistor. This constant voltage output can be compared against a voltage obtained from a voltage divider circuit which provides an output that varies in accordance with variations in the power supply. The voltage level detector circuit is particularly useful in microprocessors and microcomputer integrated circuit chips.