SHALLOW TRENCH ISOLATION

A METHOD FOR FORMING AN ISOLATION STRUCTURE (164) ON A SEMICONDUCTOR SUBSTRATE (102) INCLUDES OPENING A PORTION OF A PAD OXIDE LAYER (104) OVERLYING THE SUBSTRATE (102) USING A PROCESS GAS INCLUDING AN ETCHANT GAS AND A POLYMER-FORMING GAS. A PORTION OF THE SUBSTRATE (102) EXPOSED BY THE OPENING STE...

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Bibliographic Details
Main Authors WAN GIE LEE, CHOONG SHIAU CHIEN, CHANG GI LEE, CH'NG TOH GHEE, HITOMI WATANABE, SANG YEON KIM, CHIEW SIN PING, CHARLIE TAY, INKI KIM, NAOTO INOUE, MIN PAEK, RAMAKRISHNAN RAJAGOPAL
Format Patent
LanguageEnglish
Published 14.05.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A METHOD FOR FORMING AN ISOLATION STRUCTURE (164) ON A SEMICONDUCTOR SUBSTRATE (102) INCLUDES OPENING A PORTION OF A PAD OXIDE LAYER (104) OVERLYING THE SUBSTRATE (102) USING A PROCESS GAS INCLUDING AN ETCHANT GAS AND A POLYMER-FORMING GAS. A PORTION OF THE SUBSTRATE (102) EXPOSED BY THE OPENING STEP IS ETCHED TO FORM A TRENCH (118) HAVING A FIRST SLOPE (170) AND A SECOND SLOPE (172). THE FIRST SLOPE (170) IS GREATER THAN 45 DEGREES, AND THE SECOND SLOPE (172) IS LESS THAN 45 DEGREES. THE TRENCH (118) IS FILLED TO FORM THE ISOLATION STRUCTURE (164).
Bibliography:Application Number: MY2004PI00236