WAFER SCALE OR FULL WAFER MEMORY SYSTEM, PACKAGE, METHOD THEREOF AND WAFER PROCESSING METHOD EMPLOYED THEREIN

• Main Authors: NAKAMURA, HISASHI, SASAKI, KEIJI, MISHIMAGI, HIROMITSU, SAHARA, KUNIZO, SAKUTA, TOSHIYUKI, ITO, KAZUYA, HOMMA, MAKOTO, TAZUNOKI, MASANORI, OTSUKA, KANJI, SATOH, TOSHIHIKO, KAWAMURA, MASAO, ENOMOTO, MINORU, KUROSAWA, HINOKO, KURODA, SHIGEO
• Format: Patent
• Language: English
• Published: 23.09.1996
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To package large scale semiconductor wafers (101) a packaging device (103) is provided which engages the wafers (101) e.g. by supporting members (105A,105B) and hence supports the wafers (101) in a spaced-apart stack. Preferably, the supporting members (105A,105B) include means for making electrical contact between the device (103) and the wafers (101). The device (103) may be in the form of a pillar extending through holes (102) in the wafers (101). Alternatively (Fig. 1D), the device (103) may be divided into sections which are interposed between adjacent wafers (101) or (Fig. 2A) may have a plurality of pillars (201) which engage the edges of the edges of the wafers (203). Thus large scale wafers can be stacked, and electrical contact made to semiconductor devices on the wafers in the stack.