MEMORY

내용없음 A memory (10) for performing read cycles and write cycles, having memory cells (50) located at intersections of word lines (52) and complementary bit line pairs (54). In the read cycle, a column decoder (16) decodes a column address to couple selected bit line pairs (54) to global data lines (3...

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Bibliographic Details
Main Author BADER, MARK D
Format Patent
LanguageEnglish
Korean
Published 11.09.1996
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:내용없음 A memory (10) for performing read cycles and write cycles, having memory cells (50) located at intersections of word lines (52) and complementary bit line pairs (54). In the read cycle, a column decoder (16) decodes a column address to couple selected bit line pairs (54) to global data lines (30) for subsequent output. In the write cycle, write global data lines (40) receive input data signals and couple them to selected bit line pairs (54) for storage in memory cells (52). After the write cycle, equalization of bit lines (56, 58) is achieved partly by bit line loads (60) coupled to each bit line (56, 58), and partly by write data line loads (80) located in the column decoder (16). The write data line loads (80) can be shared by several bit line pairs (54) and thereby be sized larger than if located only on the bit line pairs (54), and can equalize the bit lines (56, 58) faster than if located on the global data lines (32, 34).
Bibliography:Application Number: KR19900013586