SEMICONDUCTOR MEMORY DEVICE

The memory device of this invention includes a plurality of memory cell blocks each having a plurality of memory cells disposed in a matrix form. A memory cell selector selects a predetermined number of the memory cells in each memory cell block in accordance with external address signals. A sense a...

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Bibliographic Details
Main Authors NAKAMURA, TAKENORI, SUZUKI, YOUICHI
Format Patent
LanguageEnglish
Korean
Published 20.03.1996
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The memory device of this invention includes a plurality of memory cell blocks each having a plurality of memory cells disposed in a matrix form. A memory cell selector selects a predetermined number of the memory cells in each memory cell block in accordance with external address signals. A sense amplifier unit amplifies data read from the selected memory cells for data read. A data output unit outputs the data amplified by the sense amplifier unit. A block selector selects a desired one or more of the memory cell blocks as data write blocks for data write. A data write unit writes data in the selected memory cells in the selected blocks. A sense amplifier controller supplies, during the data write, a signal to the sense amplifier unit to make the sense amplifier unit inactive, and during the data read supplies a signal to the sense amplifier unit to make the sense amplifier unit active.
Bibliography:Application Number: KR19920003697