SEMICONDUCTOR MEMORY

• Main Authors: HURUYAMA, DORU, KUSHIYAMA, NATSUKI, NUMATA, GENJI
• Format: Patent
• Language: English; Korean
• Published: 25.01.1996
• Edition: 6
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A semiconductor memory comprises a dynamic type memory cell array (10) arranged to form a matrix and provided with word lines (WL1 to WLm) commonly connected to memory cells (MC) of respective columns and bit lines (BLl through BLn) commonly connected to memory cells of respective rows, a dummy cell section (11) having a first set of dummy word lines (DWL) connected to respective complimentary bit line pairs (BL, /BL) of said memory cell array by way of respective first capacitances (C) and a second set of dummy word lines (/DWL) connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances (C), a dummy word line potential control circuit (15) capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers (SAl to SAn) connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.