ROW REDUNDANCY CIRCUIT WITH IMPROVED HIGH INTEGRATION AND RELIBILITY AND SEMICONDUCTOR MEMORY DEVICE THEREOF

The row redundancy circuit in a semiconductor memory device comprises: a plurality of spare cell array blocks for replacing defected normal memory cells in normal cell array blocks by spare cells; a plurality of spare decoders respectively connected to the spare cell array blocks, for driving a word...

Full description

Saved in:
Bibliographic Details
Main Author PARK, CHAN - JONG
Format Patent
LanguageEnglish
Korean
Published 21.12.1995
Edition6
Subjects
Online AccessGet full text

Cover

Loading…