ROW REDUNDANCY CIRCUIT WITH IMPROVED HIGH INTEGRATION AND RELIBILITY AND SEMICONDUCTOR MEMORY DEVICE THEREOF
The row redundancy circuit in a semiconductor memory device comprises: a plurality of spare cell array blocks for replacing defected normal memory cells in normal cell array blocks by spare cells; a plurality of spare decoders respectively connected to the spare cell array blocks, for driving a word...
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Main Author | |
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Format | Patent |
Language | English Korean |
Published |
21.12.1995
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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