ROW REDUNDANCY CIRCUIT WITH IMPROVED HIGH INTEGRATION AND RELIBILITY AND SEMICONDUCTOR MEMORY DEVICE THEREOF

• Main Author: PARK, CHAN - JONG
• Format: Patent
• Language: English; Korean
• Published: 21.12.1995
• Edition: 6
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

The row redundancy circuit in a semiconductor memory device comprises: a plurality of spare cell array blocks for replacing defected normal memory cells in normal cell array blocks by spare cells; a plurality of spare decoders respectively connected to the spare cell array blocks, for driving a word line connected to a specific spare cell in the spare cell array block if there occurs any defect in the word line connected to a normal memory cell in the normal cell array block; a plurality of fuse units respectively connected to the spare decoders, for programming a defected address if there occurs any defect in a normal memory cell; a plurality of block selecting units respectively connected to the output signals of the fuse units, for designating the position of the normal cell array block wherein a normal memory cell is defected; and a redundancy driving unit which is distanced from the normal cell array block by a predetermined distance and has an input connected to the output signals of the fuse units and an output connected to the block selecting units.