SEMICONDUCTOR MEMORY DEVICE

Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions...

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Main Authors HASHIMOTO, NAOTAGA, HANAMURA, SHOUJI, MASUHARA, TOSHIAKI, ISHIBASHI, KOUICHIRO, MORIWAGI, NOVUYUKI, UETA, GIYONOBU, MINADO, OSAMU, HONCHOU, SHIGERU, SAGAI, YOSHIO, NAGAYAMA, TOSHIAKI
Format Patent
LanguageEnglish
Korean
Published 01.09.1995
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.
Bibliography:Application Number: KR19870003628