SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANT CIRCUIT AND METHOD OF TESTING TO SEE WHETHER OR NOT REDUNDANT CIRCUIT IS USE THEREIN

• Main Authors: NAKAYAMA, AKIO, HIRAYAMA, KAZUTOSHI
• Format: Patent
• Language: English; Korean
• Published: 15.05.1995
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE:To eliminate the need for setting the connection condition of a redundant detection circuit corresponding to the pressure of the utilization of a redundant circuit at the time of manufacturing by automatically latching logic level signals into the redundant detection circuit corresponding the presence of the utilization of the redundant circuit by means of a spare row decoder activating circuit or a spare column decoder activating circuit at the time of supplying an external address signal to a semiconductor memory device. CONSTITUTION:The semiconductor memory device is provided with a spare memory cell array, spare column decoders (41-1) to (41-n) and spare row decoders (24-1) to (24-n) as the redundant circuit. The redundant detection circuits (22a-1) to (22a-n), (22b-1) to (22b-n) for inspecting the presence of the redundant circuit at the time of the completion of the semiconductor memory device respond to the specified logic level output signals from the spare row decoders (24-1) to (24-n) or the spare column decoder (41-1) to (41-n) and the specified current or voltage signal for indicating the utilization of the redundant circuit is set so as to be introduced to the prescribed external terminal 23.