METHOD OF MANUFACTURING CAPACITOR OF SEMICONDUCTOR MEMORY DEVICE

forming a polysilicon layer and heavily doped polysilicon layer in an alternation manner on an interlevel insulating layer formed on a MOS transistor formed on a substrate, to be connected to the drain or source of the MOS transistor; forming a trench on a contact region in which the drain of the MO...

Full description

Saved in:
Bibliographic Details
Main Authors KIM, YONG - BAE, KIM, BYONG - RYOL, PARK, MUN - KYU
Format Patent
LanguageEnglish
Korean
Published 15.10.1994
Edition5
Subjects
ELECTRICITY
Online AccessGet full text

Cover

More Information
Summary:forming a polysilicon layer and heavily doped polysilicon layer in an alternation manner on an interlevel insulating layer formed on a MOS transistor formed on a substrate, to be connected to the drain or source of the MOS transistor; forming a trench on a contact region in which the drain of the MOS transistor and a storage node of a capacitor are connected to each other; forming a polysilicon layer on the overall surface of the substrate to form the storage node in the trench; patterning the layers placed on the trench, selectively removing the heavily doped polysilicon layer, forming a dielectric layer on the overall surface of the substrate; and forming a plate electrode on the dielectric layer; thereby forming a fin-structure capacitor.
Bibliography:Application Number: KR19910019754