SYSTEM CONTROLLING A VARIETY OF RAMS ACCESS CHANNEL

The invention is the system for accessing shared RAM in FIFO fashion. The system comprises an enable generator outputting busy-read signal if two or more input busy-read signals are active; a control signal generator to enable selectively SRAM, address buffers, data buffers by outputting chip enable...

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Bibliographic Details
Main Author KWON, YONG - KWAN
Format Patent
LanguageEnglish
Korean
Published 15.09.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The invention is the system for accessing shared RAM in FIFO fashion. The system comprises an enable generator outputting busy-read signal if two or more input busy-read signals are active; a control signal generator to enable selectively SRAM, address buffers, data buffers by outputting chip enable, read enable, write enable, and busy signal by logical-ORing of busy-read, several memory read/write, chip select signals. Control signal generator comprises a SRAM chip enable generator (9a); a busy-signal generator (9b); a read enable generator (9c); a write enable generator (9d).
Bibliography:Application Number: KR19910017834