BUS ARBITRATION METHOD

The method arbitrates the bus in computer systems without separate arbitration logic. The method comprises the steps of: recognizing the assertion of T-REQ and INTR from the transmit state machine (8); if asserted, driving request signals A, B, D, F, H; when INTR and request signals C, E, G, I are n...

Full description

Saved in:
Bibliographic Details
Main Author SON, YONG - WAN
Format Patent
LanguageEnglish
Korean
Published 15.09.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:The method arbitrates the bus in computer systems without separate arbitration logic. The method comprises the steps of: recognizing the assertion of T-REQ and INTR from the transmit state machine (8); if asserted, driving request signals A, B, D, F, H; when INTR and request signals C, E, G, I are not asserted, starting the bus cycle by sending SEL signal from NAND gate (9) to the transmit state machine (8); when the bus cycle is completed, deasserting BUSY; inhibiting the activation of SEL by making the request B, D, F, G deasserting request C, E, G, I.
Bibliography:Application Number: KR19910025994