GATE ARRAY INTERNAL LOGIC SCAN SYSTEM

The system improves the test accuracy of the logic scanner system to add the gate array test circuit. The system comprises; multiple register loops (17-19) set for the internal loop back test; a first multiplexer (16) outputting the multiple register signals; decoding units (15,20) providing the sel...

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Bibliographic Details
Main Author SON, YONG - WAN
Format Patent
LanguageEnglish
Korean
Published 28.07.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The system improves the test accuracy of the logic scanner system to add the gate array test circuit. The system comprises; multiple register loops (17-19) set for the internal loop back test; a first multiplexer (16) outputting the multiple register signals; decoding units (15,20) providing the selection control signal of the multiplexer; a test logic (1) set in the gate array; a logic control unit (14) connected with a microprocessor (3); and a counter unit outputting the counter results to the logic control unit.
Bibliography:Application Number: KR19910019498