MANUFACTURING METHOD AND APPARATUS OF SEMICONDUCTOR MEMORY

• Main Authors: YONEHARA, KAZUO, SAITO, KOJI, TAKIZAWA, MAKOTO, NOBORI, KAZUHIKO, ISHIKURO, SHIGEFUMI, IWASE, DAIRA, NIKAWA, SATOSHI, ASANO, MASAMICHI
• Format: Patent
• Language: English; Korean
• Published: 08.11.1993
• Edition: 5
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array, wherein: each spare memory cell constituting the spare memory cell array includes a first transistor (T3) selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor (T1) connected between the interconnection between the first transistor (T3) and fuse (F1) and a ground; and the fuse (F1) is selectively blown by flowing a blowing current through the fuse (F1) by selecting the second transistor (T1) through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor (T1) of the spare memory cell which is made conductive upon selection through the write line and the blowing current flows through the fuse (F1), is adapted to be higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including the manufacturing steps of implanting impurity ions of one conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of the other conductivity type reverse to the one conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of the conductivity type reverse to the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.