LAYOUT OF SIGNAL LINE IN THE SEMICONDUCTOR IC

This is about the signal line setting method of semiconductor integrated circuit, specially about one which blocks the influence of noise by the parasitic capacitance. This method applies to a case without needing the device line connected to device(40). The signal line area is shown by discerning t...

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Bibliographic Details
Main Author LEE, JONG - RYOL
Format Patent
LanguageEnglish
Published 07.10.1993
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:This is about the signal line setting method of semiconductor integrated circuit, specially about one which blocks the influence of noise by the parasitic capacitance. This method applies to a case without needing the device line connected to device(40). The signal line area is shown by discerning the first, the second and the third stages (41)(42)(43) in the order of distance away from the driver(4). The signal line area in the first stage(41) arrayed in the state at the first interval(s1), and the second stage is at the second interval ,and the third stage is at the third interval. The interval of the first, the second and the third have the characteristic as s1<s2<s3.
Bibliography:Application Number: KR19900020285