MANUFACTURING METHOD OF FET
A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the pol...
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Main Authors | , |
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Format | Patent |
Language | English Korean |
Published |
04.03.1993
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Edition | 5 |
Subjects | |
Online Access | Get full text |
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Summary: | A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate. |
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Bibliography: | Application Number: KR19840002911 |