DECODING METHOD OF SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device has a memory cell matrix in which a plurality of memory cells are connected in rows by work lines and in columns by bit lines. The device comprises cell row groups each of which is formed by memory cell rows commonly activated by several row address signals at a first s...

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Bibliographic Details
Main Author ISOBE, MITSUO
Format Patent
LanguageEnglish
Published 26.12.1992
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A semiconductor memory device has a memory cell matrix in which a plurality of memory cells are connected in rows by work lines and in columns by bit lines. The device comprises cell row groups each of which is formed by memory cell rows commonly activated by several row address signals at a first selection stage, a row group selection decoder having the smallest decoding circuits as a first stage decoder each connected to the row group(s) by first stage word line and commonly activating any group(s) at the first row selection stage by several row address signals, and a row selection decoder as a second stage decoder having the smallest decoding units entirely provided in the matrix and each activating any cell row(s) at a second selection stage by remaining row address signals.
Bibliography:Application Number: KR19890010406