SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDUNT BLOCK

The memroy device comprises several normal memory blocks (NB) containing conly normal memory cells and a redundant memory block (RB) containing only redundant memory cells. A block decoder (18) selects one of the normal blocks (NB) in response to first address signals. The redundant column decoder (...

Full description

Saved in:
Bibliographic Details
Main Authors BYUN HYUN-KEUN, CHOI KYU-HYUN, LEE JONG-RYUL, KWAK CHUNG-KEUN
Format Patent
LanguageEnglish
Published 31.07.1991
Edition5
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:The memroy device comprises several normal memory blocks (NB) containing conly normal memory cells and a redundant memory block (RB) containing only redundant memory cells. A block decoder (18) selects one of the normal blocks (NB) in response to first address signals. The redundant column decoder (RCD) selects normal memory cells according to the output of the block decoder and second adress signals. Normal columm and row decoders (NCD,NRD) are disabled by a redundant control clock generator (22) when a defective normal memory cell is addressed. One of the decoders (NCD) is enabled by the block decoder (18) when a defect-free normal memory cell is addressed.
Bibliography:Application Number: KR19890006959