APPARATUS FOR GENERATING SYCHRONOUS AND SYSTEM CLOCK PULSES FOR DIGITAL SIGNAL CONVERTER

The clock generator supplying constant dual system clocks of 1.544 Mb/s and 2.048 Mbs/s comprises a first selector (10) selecting one clock source from the inner clocks, a second selector (20) selecting one clock source from output of the first selector and outer clock, a digital phase lock loop cir...

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Bibliographic Details
Main Authors KIM JAE-KEUN, KO JE-SOO, KIM HO-KON
Format Patent
LanguageEnglish
Published 31.07.1991
Edition5
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:The clock generator supplying constant dual system clocks of 1.544 Mb/s and 2.048 Mbs/s comprises a first selector (10) selecting one clock source from the inner clocks, a second selector (20) selecting one clock source from output of the first selector and outer clock, a digital phase lock loop circuit (40) generating a first (8 KHz), a second (1.544 MHz), a third (2.048 MHz), and a fourth (4.096 MHz) clocks synchronised to the selected clock of the second selector, and an analog PLL circuit (50) removing the jitter components contained in the second, third, and fourth clocks to use them as the trunk transmission clock, a circuit (30) checking the system clock loss, and a switch (60) transfering the clock generator to the standby system clock generator when it is in failure.
Bibliography:Application Number: KR19880017358