DEADLOCK DETECTION AND RESOLUTION SCHEME

• Main Authors: GRINN JAMES M, HEPLER EDWARD L, BRAHM DAVID J, SULLIVAN JOHN M
• Format: Patent
• Language: English; Korean
• Published: 27.06.1991
• Edition: 5
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

In a communication system which includes a plurality of stations interconnected for communications by a first bus, a second station includes a device, such as a processor, and a resource, such as a memory or a peripheral unit, interconnected for communication by a second bus. An interface mechanism connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses. Deadlock detection circuitry detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource. Deadlock resolution circuitry responds to deadlock detection by disconnecting the device from the second bus to allow the first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource. If the device is operating under program control, the deadlock detection and resolution are transparent to the program.