APPARATUS FOR ADRESSING SEMICONDUCTOR ARRARYS IN A MAIN MEMORY UNIT CONSECUTIVE SYSTEM CLOCK CYCLES

Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling...

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Bibliographic Details
Main Authors NATUSCH PAUL J, HENRY JOHN F.JR, SENERCHIA DAVID C
Format Patent
LanguageEnglish
Korean
Published 27.06.1991
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.
Bibliography:Application Number: KR19870700878