NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device comprises a cell transistor (32) formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer (CG), a first selecting transistor (31) formed of an MOS transistor, whose gate is connected...

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Bibliographic Details
Main Authors SHIGEMATSU TOMOHISA, MARUYAMA TADASHI, SUZUKI YASOJI, YOSHIJAWA MAGOTO, WADA YUKIO
Format Patent
LanguageEnglish
Korean
Published 18.02.1991
Edition5
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A nonvolatile semiconductor memory device comprises a cell transistor (32) formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer (CG), a first selecting transistor (31) formed of an MOS transistor, whose gate is connected to a read gate line layer (RG), whose source-drain path is connected at one end to a read line layer (RL), and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor (32) formed of an MOS transistor, whose gate is connected to a write gate line layer (WG), whose source-drain path is connected at one end to a write line layer (WL), and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage (Vcc) of 5 V can be supplied to the read line layer (RL) in the read mode.
Bibliography:Application Number: KR19880000843