CHAMBER ARRANGEMENTS SEMICONDUCTOR PROCESSING SYSTEMS HAVING CHAMBER ARRANGEMENTS AND RELATED MATERIAL LAYER DEPOSITION METHODS

• Main Authors: KAJBAFVALA AMIR, LU YANFU, DEMOS ALEXANDROS, MISKIN CALEB, MURALI ARUN
• Format: Patent
• Language: English; Korean
• Published: 07.03.2024
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; MEASURING; MEASURING QUANTITY OF HEAT; MEASURING TEMPERATURE; METALLURGY; PHYSICS; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; TESTING; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR

챔버 장치는 상부 및 하부 벽을 갖는 챔버 몸체를 갖는다. 기판 지지부는 챔버 몸체의 내부에 배열되고 회전 축에 대해 회전하도록 지지된다. 상부 히터 요소 어레이는 상부 벽 위에 지지되고 하부 히터 요소 어레이는 하부 벽 아래에 지지된다. 고온계는 상부 히터 요소 어레이 위에 지지되고, 챔버 몸체의 내부에 광학적으로 결합되고, 상부 히터 요소 어레이에 작동 가능하게 연결된다. 열전대는 챔버 몸체의 내부에 배열되고, 기판 지지부와 기계적으로 밀접 접촉하고, 하부 히터 요소 어레이에 작동 가능하게 연결된다. 반도체 처리 시스템 및 재료 층 증착 방법이 또한 설명된다. A chamber arrangement has a chamber body with upper and lower walls. A substrate support is arranged within an interior of the chamber body and supported for rotation about a rotation axis. An upper heater element array is supported above the upper wall and a lower heater element array supported below the lower wall. A pyrometer is supported above the upper heater element array, is optically coupled to the interior of the chamber body, and is operably connected to the upper heater element array. A thermocouple is arranged within the interior of the chamber body, is in intimate mechanical contact with the substrate support, and is operably connected to the lower heater element array. Semiconductor processing systems and material layer deposition methods are also described.