DISPLAY APPARATUS AND MULTI SCREEN DISPLAY APPARATUS USING THE SAME

• Main Authors: JAEWOO PARK, JINYEONG KIM, HANSEOK KIM
• Format: Patent
• Language: English; Korean
• Published: 22.12.2023
• Subjects: ADVERTISING; BASIC ELECTRIC ELEMENTS; CRYPTOGRAPHY; DISPLAY; DISPLAYING; EDUCATION; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; LABELS OR NAME-PLATES; PHYSICS; SEALS; SEMICONDUCTOR DEVICES; SIGNS

본 출원은 최소화된 베젤 영역을 갖는 표시 장치 및 이를 이용한 멀티 스크린 표시 장치를 제공하는 것으로, 표시 장치는 복수의 데이터 배선과 복수의 게이트 배선에 의해 정의되는 픽셀 영역에 마련된 복수의 서브 픽셀 및 복수의 데이터 배선과 일대일로 연결된 데이터 패드부를 포함하는 표시 기판, 및 복수의 데이터 배선과 일대일로 연결되는 복수의 데이터 라우팅 배선을 가지면서 데이터 패드부에 부착된 데이터 라우팅 필름을 포함하며, 데이터 라우팅 필름은 데이터 패드부와 표시 기판의 일측변 및 데이터 패드부와 중첩되는 표시 기판의 후면을 둘러싸도록 표시 기판에 직접적으로 밀착될 수 있다. Disclosed is a display device and a multi-screen display device using the same, which include a minimized bezel area. The display device includes a display substrate (10) including a plurality of unit pixels (UP) having a plurality of subpixels (SP), respectively provided in a plurality of subpixel areas defined by a plurality of data lines (DL) and a plurality of gate lines (GL), and a data pad part (DPP) connected to each of the plurality of data lines (DL) in a one-to-one relationship and a plurality of data routing lines (DRL) respectively connected to the plurality of data lines (DL), wherein the plurality of unit pixels (UP) are arranged along a first axis direction (X) at a reference pixel pitch (P) being a distance between center portions of two adjacent unit pixels (UP) along the first axis direction (X), wherein a distance along the first axis direction (X) between a center portion of each of the plurality of unit pixels (UP) and an outer side surface of the display substrate (10) is equal to or less than half of the reference pixel pitch (P), wherein each of the plurality of subpixels (SP1, SP2, SP3) comprises: a pixel circuit (PC) configured to be electrically connected to the gate line (GL) and the data line (DL); a light emitting device (150) configured to be electrically connected to the pixel circuit (PC); and a planarization layer (160) configured on the pixel circuit (PC) to cover the light emitting device (160), and wherein the light emitting device (150) is surrounded by the planarization layer (160).