어레이 기판 및 디스플레이 장치

• Main Authors: LIU LIBIN, LU JIANGNAN, FENG YU
• Format: Patent
• Language: Korean
• Published: 03.11.2023
• Subjects: ADVERTISING; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION; BASIC ELECTRIC ELEMENTS; CRYPTOGRAPHY; DISPLAY; EDUCATION; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PHYSICS; SEALS; SEMICONDUCTOR DEVICES

어레이 기판이 제공된다. 어레이 기판의 각각의 화소 구동 회로가 구동 트랜지스터, 저장 커패시터, 그리고 복수의 제2 게이트 라인들 중 각각의 제2 게이트 라인에 연결되는 게이트 전극, 저장 커패시터의 제1 커패시터 전극에 연결되는 제1 전극, 제1 리셋 트랜지스터의 제2 전극에 연결되는 제2 전극을 갖는 트랜지스터를 포함하며, 트랜지스터는 제1 리셋 트랜지스터를 통해 리셋 신호를 수신하도록 구성된다. 구동 트랜지스터의 활성층과 트랜지스터의 활성층은 적어도 절연층에 의해 서로 이격된다. 구동 트랜지스터의 활성층은 제1 반도체 재료를 포함한다. 트랜지스터의 활성층은 제1 반도체 재료와는 상이한 제2 반도체 재료를 포함한다. An array substrate and a display panel thereof, and a display device. The array substrate comprises a substrate (300) and multiple sub-pixels formed on the substrate (300), wherein the sub-pixels comprise pixel circuits, the pixel circuits comprise multiple transistors, and the multiple transistors comprise at least one oxide transistor. The array substrate further comprises an oxide semiconductor layer (340) which is formed on the substrate (300), wherein the oxide semiconductor layer (340) comprises a channel region of the oxide transistor; a first planarization layer (108) which is formed on the substrate (300) and covers at least a part of the oxide semiconductor layer (340), wherein the first planarization layer (108) has a recessed region (108a), at least a part of the orthographic projection of the recessed region (108a) on the substrate (300) is provided with an annular pattern at the outer side of the orthographic projection of the channel region of the oxide transistor on the substrate, the annular pattern is an annular through hole or an annular groove, and the orthographic projection of the annular pattern on the substrate surrounds the orthographic projection of the channel region of the oxide transistor on the substrate; and a blocking portion (3710) which is formed on a side of the first planarization layer (108) away from the substrate (300), wherein at least a part of the orthographic projection of the blocking portion (3710) on the substrate (300) is overlapped with the orthographic projection of the channel region covering the oxide transistor on the substrate, the orthographic projection of the blocking portion (3710) on the substrate is overlapped with at least a part of the orthographic projection of the recessed region on the substrate, and a recessed region of the annular pattern is filled with a part of the blocking portion (3710). The solution can improve the stability of a product.